sequential circuit造句
例句與造句
- Verification of sequential circuit design based on obdd
時序電路設計的驗證 - Asynchronous transmission sequential circuit
傳送信號減衰 - Asynchronous sequential circuit
異步時序電路 - Autonomous sequential circuit
自激時序電路 - We also develop a new word - level fault parallel fs algorithin for synchronous sequential circuits
接著又開發了一個新的單機字級故障并行fs算法。 - It's difficult to find sequential circuit in a sentence. 用sequential circuit造句挺難的
- The content of this thesis just is parallel atpg algorithlms and it prototype system for non - scan synchionous sequential circuits
本文的研究內容正是面向非掃描同步時序電路的并行atpg算法。 - Most of vlsi circuits are sequential circuits . sequential circuits can be simulated by symbolic finite state machine ( fsm )
Vlsi系統中大部分是時序電路，時序電路可以用符號化的有限狀態機( finite - state - machine ，簡稱fsm )來模擬。 - Although some scholars have done lots of work on the test generation of the digital circuits , it is still a well - known puzzle to test sequential circuits
雖然各國學者在數字電路測試生成上已做了大量的工作，時序電路的測試生成仍然是公認的難題。 - The sy - stem had different requirements on time sequence in high - speed clock and low - speed clock situations , which resulted in the complexity of the sequential circuit
在高速時鐘和低速時鐘的情況下，系統有不同的時序要求，這就決定了時序電路的復雜性。 - The international standard sequential circuits iscas ' 89 ( addendum ' 93 included ) is used to verify the algorithm , and the results are better than other algorithms "
采用國際標準時序電路iscas ’ 89 (包括addendum ’ 93 )進行了算法驗證，取得了優于文獻中其它算法的結果。 - Optimize synchronous sequential circuit with retiming was introduced by leiserson and saxe in 1983 , and retiming optimizational algorithm was summarized comprehensively in 1991
Leiserson和saxe于1983年提出了利用重定時優化同步時序電路，并于1991年對重定時優化算法做了全面的總結。 - The automatic test vector generation method based on fault simulation is described , and the whole procedure of atpg of sequential circuits is analyzed , fault simulator - hope as an example
本文闡述了基于模擬的自動測試生成方法，以故障模擬器? hope為例分析了整個時序電路自動測試生成過程。 - In order to eliminate the sequence conflict of synchronous sequential circuit and shorten the designable time of integrated circuits , the algorithms of retiming is deeply researched in this paper
本文對重定時算法進行了深入研究，目的在于消除同步時序電路的時序沖突，從而縮短集成電路的設計時間。 - To avoid the idleness state and the corresponding power dissipation in sequential circuits , a clock gating technique and a multi - code assignment using redundant state is adanced to reduce power dissipation
為抑制時序電路中的冗余現象，研究了時序電路的門控時鐘技術，并利用t型觸發器進行時序電路設計。 - Base on the existing synchronous sequential circuits fault simulator - hope , the test vector generation method of sequential circuits based on ant algorithm is systematically researched firstly
本文在同步時序電路故障模擬器? hope的基礎上，率先對基于螞蟻算法的時序電路測試矢量生成方法作了系統的開拓性研究。
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